1. Field of the Invention
The claimed inventions relate in general to Rambus DRAM arrangements. More specifically, the claimed inventions feature, at least in part, an improved Rambus DRAM arrangement having improved power save operation that is not restricted in using time and has a short setting time. It operates by forcibly compensating for loss of stored value of a capacitor of a memory cell when a power save mode is changed to a normal mode.
2. General Background and Related Art
In general, a Rambus DRAM has various operational modes for low power system operation, such as an active mode, a standby mode, a nap mode and a power down mode. The four modes can be organized based on a power reduction and a transmission time of the Rambus DRAM.
In the active mode, the Rambus DRAM is prepared to transmit data at any time. The Rambus DRAM consumes more power in the active mode than it does in any of the other modes.
In a general DRAM system all memory banks of each device perform a read/write operation according to an access command. In contrast, a Rambus DRAM system performs the read/write operation through one device, while the other devices are operated in a low power state.
The Rambus DRAM is automatically changed to standby mode in a last stage of its operation. When a device address is decoded by a request packet, all the Rambus DRAMs are changed to the standby mode, except for one device corresponding to the request. The device returns to the standby mode when finishing the read/write operation.
That is, the Rambus DRAM has a tendency to return to standby mode. Only the selected Rambus DRAM changes to active mode while the other Rambus DRAMs remain in the standby mode. As a result, power consumption is reduced.
In addition, power consumption can be reduced by changing the mode of operation of one or more Rambus DRAMs to nap mode. Nap mode operation consumes less power than standby mode operation, and is more rapidly changed to active mode than the power down mode. Whenever the system does not perform the read or write operation, the Rambus DRAM is changed to nap mode, thereby remarkably reducing power consumption. When one or more Rambus DRAMs are changed to the power down mode, power can also be considerably saved. For example, such a mode is applied to a portable computer.
FIG. 1 is a block diagram illustrating a conventional Rambus DRAM having a power save function. The Rambus DRAM includes a packet controller 20 for analyzing a packet ctrl_PKT applied from an external channel, and generating a control signal (op_code signal and cntrl signal) for controlling a power mode. A power mode controller 30 generates power mode signals (nap mode signal Nap and power down mode signal PDN) and a self refresh enable signal self_refresh_en according to the control signal (op_code signal and cntrl signal) from the packet controller 20. A delay locked loop 40 controlled according to the power mode signals, receives a clock signal clk_in from the external channel, detects a phase difference between the clock signal clk_in and a clock signal clk_out used in a semiconductor memory device, adjusts the two clock signals to have an identical phase, and generates to the power mode controller 30 a lock signal indicating that the mode can be changed to a normal mode. A memory core 10 has memory cells 14 and a refresh counter 12 controlled according to the self refresh enable signal self_refresh_en.
In the conventional Rambus DRAM, in the power save mode, a value stored in a capacitor of a memory cell is lost due to leakage current after an extended period of time. A setting time of a few hundred ns to a few xcexcs is required to set up the value. In the nap mode using the data value stored in the capacitor of the memory cell, an exit time is about 100 ns and an allow time is just a few ns. However, power of 4 mA is consumed. In the power down mode, the allow time is not restricted and power of 1 mA is consumed, but the exit time reaches a few xcexcs.
As a result, the conventional Rambus DRAM using the nap mode and the power down mode requires a long setting time to set up the capacitor value of the memory cell lost due to the leakage current in the power save mode, has the restricted using time, and increases power consumption.
Some of the claimed inventions feature a Rambus DRAM having a power save function which is not restricted in using time and has a short setting time, by forcibly compensating for a lost capacitor value in a memory cell to have a predetermined value, when a power save mode is changed to a normal mode.
A Rambus DRAM constructed and arranged in accordance with the principles of the claimed inventions includes a memory core unit having a plurality of memory cells and a refresh counter. A packet controller analyzes a packet control signal applied from an external channel, and generates a control signal for controlling a power mode. A power mode controller generates each power mode signal and a self refresh enable signal for controlling the operation of the refresh counter according to the control signal. A delay locked loop (DLL) is controlled by the power mode signals and adjusts a phase difference between a clock signal applied from the external channel and a clock signal used in a semiconductor memory device, and provides to the power mode controller a signal indicating that the mode of operation can be changed to a normal mode.
The control signal includes an OP code signal for regulating operation modes and signals for controlling power modes. The OP code signal is preferably a two bits signal (but other bit arrangements are possible). According to the two bit signal arrangement, the mode cannot be changed to a power save mode when the two bits are xe2x80x9800xe2x80x99, the mode is changed to a power down mode, when they are xe2x80x9801xe2x80x99, the mode is changed to a nap mode when they are xe2x80x9801xe2x80x99, and the mode is changed to a doze mode when the two bits are xe2x80x9811xe2x80x99.
The power mode signal includes a nap mode signal, a power down mode signal and a doze mode signal. The delay locked loop includes a phase detector and a mixer for receiving the clock signal from the external channel, detecting the phase difference between the clock signal applied from the external channel and the clock signal used in the semiconductor memory device, and mixing the clock signals. A clock amplification unit amplifies the output signal from the phase detector and mixer. A clock buffer unit buffers and outputs the output signal from the clock amplification unit. A control unit receives the power mode signal from the power mode controller, and controls the operation of each circuit. A bias generation unit provides bias signals respectively to the phase detector and mixer, the clock amplification unit and the clock buffer unit according to the power mode signal from the control unit. A duty cycle compensation unit controls the operation of the phase detector and mixer, the clock amplification unit and the clock buffer unit in order to compensate for the phase difference between the clock signal applied from the external channel and the clock signal used in the semiconductor memory device, and compensate for a current value lost in a cell capacitor of the memory core according to the power mode signal from the control unit.
Our Rambus DRAM arrangement includes a bias generation unit operable in normal mode, nap mode and doze mode, when the mode cannot be changed to the power save mode. The duty cycle compensation unit includes a capacitance compensation circuit for compensating for the current value lost in the cell capacitor of the memory core. The capacitance compensation circuit is operated in the power down mode and doze mode. The self refresh enable signal is enabled in the nap mode, doze mode and power down mode.